Viewing and Debugging Shaders

Shader Type

Shader type.

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SIMD

Number of threads in a warp. The value can be 32 or 64. The compiler selects a value based on the shader type and content.

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Number of general purpose register

Number of used general-purpose registers.

Registers affect the number of concurrent warps, which affects the GPU execution efficiency.

SIMD32:

≤ 64 (Excellent)

≤ 84 (Good)

> 128 (Poor)

SIMD64:

≤ 32 (Excellent)

≤ 42 (Good)

> 64 (Poor)

Number of constant register

Number of used constant registers. It usually includes literal constants, uniform modifier variables, and built-in variables.

Constant registers are used to reduce UBO access or accelerate the computation between constants.

Check whether the value of this indicator is close to the upper limit (vs/fs: 512, cs: 1024). If the value reaches the upper limit, you are advised to reduce the UBO size or manually combine constants for computation.

Private memory usage per-thread (Byte)

Size of the private memory used by each thread, in bytes. Generally, the local array variable is used in the shader or there are too many variables, resulting in register spilling.

The efficiency of accessing variables with the private memory is low, which greatly affects the performance.

1. Avoid non-constant subscript indexes of local array variables. 2. Reduce the number of local array variables or the lifetime of variables, to avoid register spilling.

Nesting depth

Branch nesting depth.

GPU execution requires additional units to record and restore branch information, and the branch record unit is shared within the warps. Therefore, too deep branch nesting may lower warp concurrency.

≤ 4 (Excellent)

≤ 8 (Good)

> 12 (Poor)

Estimated warp concurrency

Number of warps delivered in an execution unit at the same time (warp concurrency).

When the execution unit encounters data dependency which causes inter-instruction waiting, another warp can be used to improve the utilization of the execution unit.

≥ 4 (Excellent)

≥ 3 (Good)

≤ 2 (Poor)

Total instructions

Total number of instructions.

If the total number of instructions is large, the execution time of a single shader may be long. In addition, the cache of the instruction segment is affected.

Avoid oversized shaders.

Total ALU instructions

Total number of computing instructions.

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32 bit ALU instructions

Number of 32-bit computing instructions, which corresponds to full-precision computing (highp).

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16 bit ALU instructions

Number of 16-bit computing instructions, which corresponds to half-precision computing (mediump/lowp).

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16 bit ALU instructions ratio

Percentage of 16-bit computing instructions to total computing instructions.

In Maleoon 910 SIMD64, the efficiency of 16-bit computing instructions is twice that of 32-bit computing instructions. Therefore, increasing the percentage of the half-precision computing can improve the GPU execution efficiency.

It is recommended that the half-precision percentage of precision-insensitive render passes such as lighting and post-processing be 20%.

Total Control flow instructions

Number of control flow instructions.

The GPU architecture is suitable for parallel computing. Too many branches may cause thread forking in a warp, resulting in low execution efficiency. In addition, the execution efficiency of control flow instructions is lower than that of common ALU instructions.

1. Minimize the control flows in the shader. 2. Replace simple control flows with ternary operations or numeric operations. 3. Use uniform as the branch judgment condition. 4. Use constant loops for the for loop.

Total Memory instructions

Number of memory access instructions.

The memory access latency is long, which may cause low GPU execution efficiency and affect the bandwidth.

1. Combine memory access operations as much as possible to reduce memory access of invalid components or components one by one. 2. Properly arrange the sequence of memory access operations, to improve the cache hit rate.

Memory read instructions

Number of memory read instructions.

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Memory write instructions

Number of memory write instructions.

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Total texture instructions

Number of sampling instructions.

Similar to memory access instructions.

1. Control the sequence and stride of the texture size and sampling coordinates, to improve the cache hit rate. 2. The number of sampling instructions in a shader should be less than 16.